These closeups show examples of carbon nanotubes integrated into silicon chips.
This week at the International Electron Devices Meeting in San Francisco, research teams spanning academia and industry presented data on high-performance carbon nanotube transistors (CNTs) and circuits. While it may be a decade or more before these devices are integrated into products, engineers at the conference argued that the field has made tremendous progress—and that carbon nanotubes will play a key role in future systems by enabling low-power, high-performance computationthat can boost silicon chips.
CNTs are about a nanometer in diameter, and electrons sail through them. Back in 2016, researchers made the first CNT transistor that outperformed one based on silicon. However, building complex circuits and systems from CNTs has proved to be more challenging. H.-S. Philip Wong, an electrical engineer at Stanford University, says results presented by his group and others at IEDM show that CNT devices have made tremendous progress over the last few years. “Many of the fundamental problems have been solved,” he says.
At IEDM, engineers described a vision of carbon nanotube circuits that would not replace, but augment, today’s computing systems. Some hope that CNTs will play a critical role in new architectures that save energy by blending processing and memory. For example, most of the energy used in training large AI models is not spent on the calculations; it’s expended moving data between processor and memory. Doing computation within the memory itself could cut down on this energy drain.
Ways to Make Carbon Nanotubes Work for Semiconductors
There are many ways to design such a system—it can use analog memory cells (which save energy but sacrifice precision) or digital ones (which take more energy but provide better performance). At IEDM, Yibei Zhang, a Ph.D. student at Tsingua University in Beijing, described a stacked computing system that mixes analog and digital—with the help of some CNT control circuits. The bottom layer is silicon CMOS, which is topped with a layer of analog RRAM, and finished up with two layers of digital RRAM powered by carbon nanotube circuitry.
Such stacked designs are called “back-end-of-line” approaches. The CNT layers can be built on top of completed silicon CMOS using low-temperature techniques that won’t damage the underlying chip. Zhang’s team used the system to implement a neural network, and they project that it could use about 1/17th the energy and work about 119 times as fast as a conventional chip.
In a keynote at the conference, TSMC executive vice president and co-chief operating officer Yuh-Jier Mii said that CNTs “could be interesting for future scaling or to develop high performance logic in the back-end-of-line.”
To get to high performance, though, CNT transistors need further development, says Shengman Li, a postdoc at Stanford University. She’s part of a team that’s collaborating with TSMC to do just that. Circuits like the ones from the Tsingua group are made up of tangled networks of the nanomaterial. Engineers can get a lot of mileage from these imperfect transistors—in 2013, Li’s advisors Wong and Subhasish Mitra made an entire computer based on such devices. But when engineers can perfect the design and fabrication of aligned, single-nanotube transistors, they expect greater performance gains.
Finishing Touches for CNTs
Two papers presented at IEDM focused on such fine-tuning. Yi-Fan Liu of Peking University described his team’s creation of high performance CNT devices with record breaking electronic properties. Thanks to careful engineering of the device’s gate interface, his team created arrays of CNT transistors with a high current and record-breaking transconductance, a figure that relates the voltage applied to a transistor to its output current. Transconductance tells engineers how energy efficient and speedy a transistor is.
“This surpasses the maximum transconductance of silicon CMOS for the first time,” Liu said. Their process entails pre-treating a wafer coated with aligned CNTs with a hafnium-containing compound, before directly growing the gate dielectric over the nanotubes using atomic-layer deposition.
The Stanford University and TSMC group also focused on their chemical recipes. Stanford’s Li presented their methods for doping N-type CNT transistors. Silicon can be doped simply by mixing other atoms into the channel material—but adding atoms to two-dimensional and one-dimensional materials like CNTs would disrupt their structure.
One way to fix this problem is to put the dopants on top of the channel, rather than within it. But if the alignment of the dopants is off, the transistor’s performance suffers. Last year at IEDM, the team described their methods for making P-type CNT transistors. This week, they presented their work on N-type.
Their method ensures that the dopants are placed right over the nanotube. Thanks to this doping, the team achieved record breaking performance in CNT NMOS. Now that they have high performance transistors of both types, the Stanford team says they’ve shown that CNT CMOS can rival silicon CMOS.
But there’s more hard work ahead. Li says one of the last big things on the to-do list is for some chemists or materials scientists to perfect a method for precisely placing CNTs on a wafer. Today, engineers know how to make perfectly straight, parallel arrays of the nanomaterials, all lined up on silicon wafers like a row of pencils in a box. But the spacing between the nanotubes is uneven. When engineers can control this spacing, or pitch, they may finally be able to achieve the material’s full potential.